1. Field of the Invention
The present invention is directed to a control device with a parallel databus and to a method for the operation of the control device.
The invention is particularly directed to an electronic control device that must process a large data stream such as, for example, a control device for editing print data for a high-performance printer.
2. Description of the Related Art
A control device called an “SRA controller” (SRA: Scalable Raster Architecture) is described in the publication “Das Druckbuch—Technik und Technologie der Hochleistungsdrucker von Océ Printing Systems GmbH—Drucktechnologien”, Edition 3c, May 1998, ISBN 3-00-001019-X.
The structure of this known control device is schematically shown in FIG. 1. Such a control device 1 comprises an I/O module 2, one or more raster modules 3 and a serializer module 4. The individual modules 2 through 4 are connected to one another via a parallel databus 5. The raster modules 3 and the serializer module 4 are connected to one another via a further pixel bus 6. A high-performance printer 7 is connected to the serializer module 4.
The I/O module receives the print information from a computer device that can be a large computer system or a computer network as well. The print information is forwarded from the I/O module 2 to the raster modules 3 and the serializer module 4, whereby the raster modules 3 receive the print image information and convert it into a print image data stream that can be processed by the high-performance printer 7. These print image data streams are transmitted from the raster modules 3 via the pixel bus 6 to the serializer module 4, which forwards the data streams queued in a specific sequence and to the high-performance printer 7.
For example, the databus is a Multibus II (Multibus is a registered trademark of Intel Corp.). The Multibus II is a synchronized bus that is defined in IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II, The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, NY 10017, USA, 1988. Below, the “MULTIBUS II” is simply referred to as “multibus”.
The modules 2 through 4 of the control device 1 are respectively provided with a processor. An inter-processor communication ensues with a message transfer given systems based on the multibus, whereby messages with data packets having a predetermined length are communicated for the transfer of data.
There are two kinds of these messages given the multibus, namely what are referred to as unsolicited messages and solicited messages. The unsolicited messages can be view as “intelligent interrupts”, whereby up to 255 interrupt sources (the number of valid addresses) can send an unsolicited message. 28 bytes of status information can be transmitted with an unsolicited message.
The properties of an unsolicited message are that their arrival cannot be predicted by the receiver, whereby the transmission modalities (transmission rate, data quantity, . . . ) are first negotiated with unsolicited messages (buffer request message, buffer grant message and buffer reject message).
A data transfer from the I/O module 2 to the raster modules 3 via the databus 5 is shown in a flowchart in FIG. 2. The actions that occur at the I/O module are thereby shown at the left side, and the actions that are executed at the raster module 3 are shown at the right side.
In step S1, the I/O module 2 sends a message to the raster module 3 that data are present. This message is generated by the processor of the 110 module. In response thereto, the raster module sends a corresponding message in step S2 if it needs data. This message is triggered by the processor of the raster module 2. When the I/O module 2 has received this message, the processor programs a DMA controller of the I/O module to send the requested data to the raster module and sends a buffer request message to the raster module (step S3). When the raster module can accept these data, its processor programs a DMA controller for the reception of the data and sends a buffer grant message to the I/O module (step S4).
The “negotiations ” are ended with the reception of the buffer grant message by the I/O module, and the I/O module sends a data message containing a data packet to the raster module (step S5). Such a data message is transmitted until all data have been communicated to the raster module, whereby this is checked in a step S6.
When all data have been sent to the raster module, then the data transfer is ended (S7).
The steps S2 through S6 form a solicited message (broken-line frame), whereby the negotiation (S2 through S4) with which the data are requested is implemented with unsolicited messages. The individual messages of the steps S2 through S4 are respectively generated by the processors of the modules 2, 3.
The above-described interprocessor communication with a message transfer is described under the heading “Message Passing” in the publication by F. Mayer et al., “Message Passing-Protokolle in einem verteilten heterogenen Multibus-II-Mehrrechnersystem” Automatisierungstechnische Praxis—ATP DE, Oldenburg Verlag, Munich, Volume 37, No. 12, pages 42-44, 46-50, XP000542307, ISSN: 0178-2320.
Publish ed PCT Patent Application WO-A-91/06058 discloses a memory and data bank system for storing documents in the form of image data that comprises a memory processor unit connected to a databus that works according to the Multibus II protocol and, accordingly, implements the above-described method steps S1 through S7 in the data transfer. This memory processor unit is provided with an ADMA controller that, following the negotiation phase (steps S2 through S4), automatically implements the transmission of the messages (steps S5 and S6).
What are referred to as DMA controllers are known for controlling the read-in and output of memory signals. Their typical structure and functioning are described, for example, in the publication by Tietze, Schenk, “Halbleiter-Schaltungstechnik”, Springer-Verlag (1985), pages 672-675. Typical applications and functions of DMA controllers are cited in the publication by Messmer, “PC-hardware”, Addison-Wesley, 3rd Edition (1995), pages 515-516.
German Patent Document DE-T2-38 52 378 discloses a mechanism and a method for opposite flow control in a bus system, whereby the bus system is controlled with a bus administrator. In this known bus system, specific bus messages are employed in order to inform a process executing on a bus unit about a result or about an unanticipated input of another bus unit. The bus unit that receives the message knows immediately to where the message must be forwarded, instead of having to derive where the message is to be forwarded from the sender. The uninterrupted process need not return to the sender of the message in order to determine what is to be done. Since this message contains a report about what is to be done, little time is wasted determining the reason for sending the message.
A plurality of bus units can thus quickly addressed with this bus system and their processing status can be immediately modified.